Thermally induced stresses in 3D-IC inter-wafer interconnects: A combined grain-continuum and continuum approach

We introduce a hybrid grain-continuum (HGC) approach to compute stresses in structures in which grain structures are important. We demonstrate the HGC approach using thermally induced stresses in inter-wafer 3D-IC copper vias. The HGC approach is a combination of continuum representations and 3D ‘grain-continuum’ (GC) models; i.e., models in which grain boundaries are represented and tracked. Combining these two approaches allows us to focus the heavier computation load required by GC representations only where it is expected that the local stresses are of concern. We evaluate how large the GC region needs to be in our model problem; that is, how much the computations can be simplified while still achieving accurate results in a particular region of interest. It is found that the size of the transition region between the start of the GC region and the region of interest approximately corresponds to the via radius. It is found that at points, the local stresses in the GC regions significantly exceed those computed using homogeneous materials (continuum) models. Strain energy driven grain boundary migration velocities on the order of 10−8 m/h are calculated for the model system assuming a 100 K change in temperature from a stress free state. These velocities are about one order of magnitude smaller than curvature-driven motion for the same microstructure.