Ni(Pt) silicide with improved thermal stability for application in DRAM periphery and replacement metal gate devices

• A NiPt silicide stable with long 600 and 800 °C anneals, as required by DRAM periphery.
• Thermally stable silicide by pre-amorphisation + C implant + laser anneal.
• TSS successfully integrated in low voltage CMOS HKMG devices suitable for DRAM PERI.
• Thermal stability can be obtained using a spike anneal rather than a laser anneal.

In comparison to standard CMOS devices for logic applications, periphery devices for DRAMs typically require a long anneal in the temperature range between 600 and 800 °C after the silicide formation. This gives additional constraints in many process steps, in particular in the silicidation step. In this work the feasibility and optimization of a thermally stable NiPt silicide has been investigated. First, a blanket wafer study has been done showing that a thermally stable silicide (TSS) can be obtained by using a pre-amorphization implant (PAI) + C implant + laser anneal prior to the silicidation process, and a superior thermal stability can be obtained using a spike anneal rather than a laser anneal. Then, this silicide was successfully integrated in low voltage CMOS HKMG devices (Lgate down to 32 nm) without affecting the junction behavior, and featuring only minor effects on devices performance compared to a non-stabilized NiPt silicide without DRAM anneal, with applicability in a replacement metal gate process flow.

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