Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications

As transistor dimensions are reduced due to technological advances, the area constraint is becoming less restrictive, but soft error rate, leakage current, and process variation are drastically increased. Therefore, in nano-scaled CMOS technology, soft error rate, leakage current and process variation are the most important issues in designing embedded cache memory. To overcome these challenges, and based on the observation that cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper deals with new low leakage, hardened, and read-static-noise-margin-free SRAM memory cells for nano-scaled CMOS technology. These cells are completely hardened and cannot flip from particle strikes at the sensitive cell nodes. Furthermore, these new SRAM cells have free read-static-noise-margin, such that transistor mismatching, due to process variation, cannot destroy stored-data of the cells during read operation. The new cells retain their data with leakage currents and positive feedback without a refresh cycle. The basic version of new cells consists of one write port with differential write-bit-lines and one read port with differential read-bit-lines, and the improved-leakage version of new cells consists of one write port with differential write-bit-lines and one read port with a single read-bit-line. Simulation results show that the proposed cells in this work correctly operate during their read, write, and idle cycles even while considering the process variation in 22-nm technology. In the worst case, our cells have 40% lower average leakage current in comparison with conventional 6T SRAM cell without any performance degradation. Also, our cells are hardened. Thus, they have zero soft error rate.