Architecture level optimization of 3-dimensional tree-based FPGA

• This paper propose innovative design and exploration methodologies to improve the speed and density of 3D Tree-based FPGA using vertical and horizontal partitioning of programmable interconnect networks.
• An optimization methodology is proposed to optimize the programmable interconnects and TSVs using Rent based analytical wire length distribution model for 3D Tree-based FPGAs.
• This paper also address the specific issues that 3D designers will encounter dealing with design tools that are not specifically designed to meet their needs.
• This paper introduce a 3D homogeneous Tree-based FPGA, that provides 65.13% improvement in speed and reduces 36% interconnect network area compared to 2D Mesh-based industrial FPGA.

We describe a methodology to design and optimize Three-dimensional (3D) Tree-based FPGA by introducing a break-point at particular tree level interconnect to optimize the speed, area, and power consumption. The ability of the design flow to decide a horizontal or vertical network break-point based on design specifications is a defining feature of our design methodology. The vertical partitioning is organized in such a way to balance the placement of logic blocks and switch blocks into multiple tiers while the horizontal partitioning optimizes the interconnect delay by segregating the logic blocks and programmable interconnect resources into multiple tiers to build a 3D stacked Tree-based FPGA. We finally evaluate the effect of Look-Up-Table (LUT) size, cluster size, speed, area and power consumption of the proposed 3D Tree-based FPGA using our home grown experimental flow and show that the horizontal partitioned 3D stacked Tree-based FPGA with LUT and cluster sizes equal to 4 has the best area-delay product to design and manufacture 3D Tree-based FPGA.