Self-aligned metal capping layers for copper interconnects using electroless plating

Self-aligned metal capping layers formed by electroless plating, such as CoWP and NiMoP, are being investigated for a number of Cu interconnect technologies. One application is for high performance logic chips at the 45 nm node and below. The main motivation for using these capping layers is to improve electromigration lifetime, and a dielectric cap is typically used in addition to the metal cap. An improvement in electromigration lifetime of over 100X is observed with a CoWP cap, and the lifetime is independent of the direction of electron flow for dual damascene structures. A different application is for CMOS image sensors using 0.18 μm technology. For this application, the self-aligned metal cap replaces the dielectric cap, resulting in improved optical performance of the image sensor. The uniformity of the CoWP is critical for this application; if there are thin regions in the capping layer, the Cu will be exposed to the etch or strip chemistry, and via yield and reliability will be poor. For both applications the main issue with using selective capping layers is loss of selectivity, which results in high leakage currents between the metal lines. Interestingly, the leakage can actually be lower for a stand-alone CoWP cap compared to a stand-alone SiN cap, presumably due to damage associated with the SiN deposition.