Polycrystalline silicon gate originated CMOS device failure investigated by Scanning Spreading Resistance Microscopy

• SSRM is successfully applied to investigate poly-silicon originated device failure.
• Two different root causes for gate depletion are presented.
• Site specific cross section preparation is performed.
• SSRM reveals local increase in poly-Si spreading resistance.

Scanning Spreading Resistance Microscopy (SSRM) is applied to investigate single failing CMOS transistors within an integrated circuit. The failing devices are affected by increased gate depletion, and therefore, lower on-current (ION) compared to reference devices. Two different scenarios exhibiting enhanced gate depletion as root cause for single device failure are analyzed. In the first analysis case, a locally decreased dopant concentration in the poly-Si gate conductor results from an intentional micro-masking at the dopant implantation process of the gate poly-Si. In the second analysis case, the test of a different dopant activation anneal for the implanted gate poly-Si caused the sporadic formation of extremely large poly-Si grains. The specific grains appear to be much less doped, and hence lead to degraded device performance. For both analyses a site specific sample cross section preparation of the failing transistors was mandatory. As the analyzed defects are localized to a small area and surrounded by reference material the calibration of the measurement data was not necessary. The high spatial resolution and the high dynamic range in combination with the possibility to analyze not only test structures but virtually all devices of an integrated chip, make SSRM a very powerful tool for failure analysis of integrated devices.

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