A p+/p-buffer/n-epi cmos compatible high-side RESURF LDMOS transistor for Power IC applications

Realising a higher voltage application utilising bridge topologies in CMOS Power IC CMOS technology presents integration and design issues that must be solved by careful selection of the manufacturing process architecture. In this paper, we present a solution that uses a p+/p-buffer/n-epi stack to implement a 100 V RESURF N-channel LDMOS high-side compatible power transistor. The device was developed and designed onto the new substrate using TCAD industrial standard softwares (TSuprem4 and Medici). Masks were designed using the Cadence Virtuoso tool set. The physical results show good transistor characteristics compatible for high-side applications. The specific resistance, RDSon, for the new device is 175 mΩ mm2 and breakdown voltage for both high-side and low-side operations exceeds targeted 100 V. The design involved new starting material, and the test structures to measure latch-up susceptibility were also designed and manufactured. These structures were characterised and the results show minimal degradation in standard CMOS performance.