Effectiveness of wafer level test for electromigration wear out reporting in advanced CMOS interconnects reliability assessment

Electromigration (EM) copper lines reliability is assessed through standard wafer level (WL) and PL (PL) test in the present work. Since these tests are highly accelerated, one of the main questions as in all reliability studies is the effectiveness of reporting failure phenomena as they occur under use conditions. WL is known to have been intensively used for fast EM process monitoring on high volumes with elevated stress conditions. On the other hand, the PL test having less aggressive stress conditions is used in a process qualification scheme. We use the later in this study as a reference to evaluate WL test results through various processes. Thus, the present paper deals with the ability of WL in comparison to PL to effectively report reliability performances variations for different Cu lines process modifications. Results from WL reliability and PL reliability are compared in terms of lifetime variations and standard deviation evolution. Only limited correlation is found, suggesting that the failure mechanisms acting for both methods are not the same. Moreover, the results of this study highlight the need of defining new reliable EM testing structures and methods compatible with high volumes monitoring.

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