Impacts of device architecture and low current operation on resistive switching of HfOx nanoscale devices

A highly scaling feasibility of resistance memory with a via-hole structure including Ti/HfOx is demonstrated in this work. An empirical model is used to predict the correlation between the forming voltage of 5 nm-thick HfOx devices with concave configuration and their cell size. The forming voltage of the nano-devices fit well with the empirical model of dielectric breakdown. Owing to the parasitic capacitance of the support oxide, the resistance memory with a series transistor still suffers a serious current overshoot during the forming process. The first reset current in the concave device increase as the scaling down of their cell size. The 30 nm concave device with a compliance current of 0.18 mA exhibits a good operation window (ON/OFF resistance ratio >30), a satisfactory reliabilities including a thermal stability at 150 °C for 500 min lifetime and switching cycles of 104. The operation current for 50 nm concave device can be lowered to 30 μA. The first reset current in the pillar device through increasing the dielectric thickness in the parasitic capacitance can be eliminated.

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► The 30-nm nano-device with concave or pillar structure were prepared.
► The forming voltage of the nano-devices fit well the empirical model.
► The concave devices with 1T1R suffer a serious current overshoot.
► The first RESET current in the device increase as the scaling down of the device.
► The 1st reset current in the pillar device can be eliminated.