کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
543048 | 871618 | 2011 | 5 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Wafer-level three-dimensional integrated circuits (3D IC): Schemes and key technologies
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
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چکیده انگلیسی
Schemes and key technologies of wafer-level three-dimensional integrated circuits (3D IC) are reviewed and introduced in this paper. Direction of wafer stacking, methods of wafer bonding, fabrication of through-silicon via (TSV), and classification of wafer type are options for 3D IC schemes. Key technologies, such as alignment, Cu bonding, and TSV fabrication, are described as well. Better performance, lower cost, and more functionality of future electronic products become feasible with 3D IC concept application.
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ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronic Engineering - Volume 88, Issue 11, November 2011, Pages 3282–3286
Journal: Microelectronic Engineering - Volume 88, Issue 11, November 2011, Pages 3282–3286
نویسندگان
Ming-Fang Lai, Shih-Wei Li, Jian-Yu Shih, Kuan-Neng Chen,