Top down fabrication of long silicon nanowire devices by means of lateral oxidation

The process for the fabrication of devices based on a single silicon nanowire with a triangular section is presented and discussed. The top down fabrication process exploits the properties of silicon anisotropic etching for the realization of very regular trapezoidal structures, that can be uniformly reduced in controlled way by means of lateral oxidation. This allows the reproducible realization of nanowires smaller than 20 nm, and with a length of several micrometers, starting from relatively big structures that, even if electron beam lithography has been used in the present work, could be realized also by other (as optical) lithographic techniques. Nanowires are already placed between silicon contacts for electrical transport characterization. The process, compatible with the actual MOS technology, is suitable for a massive, large-scale production of silicon nanowire based devices and it allows a flexible platform for multigate and more complex structures and devices. The nanowire triangular section is a step toward the integration of three-dimensional devices. Electrical characteristics of silicon nanowire FETs, both p- and n-doped, will be reported and discussed.