Porous silicon for the development of capacitive microstructures

Macroporous silicon is developed in p-type substrates in order to extend the active surface area of the electrodes in a silicon integrated capacitive element. Some laboratory prototypes with a 3D architecture and Si/SiO2/PolySi layers have been developed. The contribution of the surface enlargement to the final capacitance is analyzed by comparing it with a 2D planar reference capacitive device. By this method, a capacitance gain of 2400% has been obtained at low frequencies with a capacitance density of 180 nF/cm2. Based on the physical microstructure, an equivalent electrical circuit of the porous capacitive element is proposed and its electrical behavior discussed.