Concurrent HCI-NBTI: worst case degradation condition for 65 nm p-channel SOI MOSFETs

Concurrent HCI-NBTI is observed to lead to worst case degradation for the Input/Output (I/O) and core logic/high speed (HS) SOI p-channel MOSFETs from 65nm technology. HC stress degradation at room temperature in I/O PMOSFET devices shows NBTI-like behavior at higher stress voltages and “combined” HCI-NBTI at lower stress voltages. On the other hand, in HS PMOSFET devices, HC degradation is shown to be induced by a combination of HCI and NBTI across the whole stress bias voltage range. Additionally, in both I/O and HS devices, higher degradation is observed for floating-body (FB) devices at high stress voltages, which becomes comparable to body-contacted (BC) devices at lower stress voltages. It is also shown that externally applied body bias plays an important role in enhancing the degradation in I/O devices but has little effect on HS devices.