Effect of SiO2 tunnel layer processes on the characteristics of MONOS charge trap devices with poly-Si channels

• Thermal SiO2 tunnel layer on poly-Si exhibits breakdown at low electric field.
• Defect assisted tunneling current exhibits in LP-TEOS SiO2 tunnel layer.
• Fast program/erase characteristics are observed in LP-TEOS SiO2 tunnel layer device.
• Program and endurance fail, which are related with IV characteristic, exhibit in thermal SiO2 device.
• Stable memory characteristics can be observed in radical SiO2 tunnel layer device.

In this study, we investigated the effect of various SiO2 tunnel layers on the characteristics of charge trap memories with Metal/SiO2/Si3N4/SiO2/n-type poly-Si (MONOS) structures. For MONOS devices, SiO2 tunnel layers were formed on poly-Si channels using thermal oxidation, radical oxidation, and LP-CVD. We investigated the characteristics of each SiO2 tunnel layer on poly-Si including breakdown, leakage current and FN tunneling. Radical SiO2 and LP-TEOS SiO2 showed larger breakdown voltages with more uniform thickness than thermal SiO2 on poly-Si channels. MONOS devices with radical SiO2 and LP-TEOS SiO2 tunnel layers showed improved program/erase (P/E) and endurance compared with thermal SiO2. In particular, the MONOS device with LP-TEOS SiO2 showed the largest memory window with the fastest P/E operation, which was attributed to enhanced defect-assisted tunneling in LP-TEOS SiO2. The endurances of MONOS devices were measured and related to the flat-band voltage shift in conjunction with trapped charge types in SiO2 tunnel dielectrics.

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