Sub-30 nm via interconnects fabricated using directed self-assembly

• Sub-30 nm via interconnects were fabricated using directed self-assembly.
• The via interconnects were integrated on a 300 mm wafer and electrically tested.
• Root cause of intra-wafer variation of via resistance is discussed.

In this study, sub-30 nm via interconnects were fabricated and fully integrated on a 300 mm wafer using directed self-assembly lithography (DSAL). They were tested electrically and initial test results are reported. DSAL was applied on the via layer, which is connecting between the lower metal layer and the upper metal layer. A trilayer resist process was utilized for preparing a guiding pattern of graphoepitaxy. Exposure dose of 193 nm immersion lithography was centered so that via size in spin-on-carbon (SOC) was just 70 nm in diameter. Poly (styrene-block-methyl methacrylate) (PS-b-PMMA) block copolymer (BCP) solution was applied on the SOC pre-pattern, and then annealed in N2 atmosphere to induce micro-phase separation. PMMA domain was finally transferred into a dTEOS oxide film as a via hole. Via interconnects were fabricated using tungsten deposition followed by CMP. Intra-wafer variation of via resistance was measured and the correlation between the via resistance and the via dimension was discussed.

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