Integration of NEMS resonators in a 65 nm CMOS technology

In this work we study the feasibility to obtain the smallest CMOS-NEMS resonator using a sub-100 nm CMOS technology. The NEMS resonators are defined in a top-down approach using the available layers of the 65 nm CMOS technology from ST Microelectronics. A combination of dry and wet etching is developed in order to release the NEMS in an in-house post-CMOS process. Two different NEMS resonators are designed: 60 nm × 100 nm polysilicon and 90 nm × 180 nm copper clamped–clamped beams. The designed polysilicon CC Beam with a length of 1.5 μm, resonates at 232 MHz and is capable to provide the same mass sensitivity than a bottom-up silicon nanowire.

In this composition are shown: (Down-Left) a picture of a ST 65 nm CMOS technology CHIP placed near a Euro coin in order to be able to compare their sizes. (Top-Left) an optical microscope image of the CHIP, where the PADS can be observed clearly and the Encapsulation–Passivation Window to release the resonators. On the right side two SEM images are shown. The top image is a M1 released resonator and the image below is a SEM image of a FIB cross section cut of a M1 resonator.Figure optionsDownload as PowerPoint slideHighlights
► The smallest CMOS-NEMS resonator using a sub-100 nm CMOS technology.
► Mass sensitivity equal to a bottom-up device.
► Study of the releasing processes.
► Copper as structural material.