Solid-state dewetting of single-crystal silicon on insulator: effect of annealing temperature and patch size

On the left is reported a schematic sequence of the fabrication steps for patterned squares on thin SOI substrate, where the thicknesses and the size of nanostructures are not in scale. is reported the standard procedure. a) Prospective view of a dewetted, square patch having 5 μm side and a hole milled at its center. The top left inset displays the shape of the etched patch via e-beam lithography and reactive ion etching. b) SEM image of 4 repetitions of the patch shown in a). c) Optical microscope dark field image of the full array (12 × 12 repetitions) of the patch shown in a) and b). The bottom-right inset shows a blow-up of an individual patch. d) Binary image obtained from the image in c). e) Statistic of patch size obtained from the image shown in d). The vertical axis is in logarithmic scale. The inset shows a blow-up of an individual patch.262