Thermal stress analysis of the low-k layer in a flip-chip package

Owing to the large size difference between the interconnection and the device, it is a challenge to model the thermal stress in a flip-chip packaging process. Multi-submodeling technology such as 4-submodel was reported to simulate the thermal stress in low-k layers. However, the numerical errors increase in the analysis due to the multiple interpolations in the method. In this work, a finite element analysis (FEA) with only one sub-model is used to predict thermal stress in the low-k layers. The model is shown in Fig. 1.