Vertically-stacked gate-all-around polysilicon nanowire FETs with sub-μm gates patterned by nanostencil lithography

► Gate-all-around vertically-stacked polySiNW FETs with gate lengths down to 100nm. ► ION/IOFF ratio up to 104, subthreshold swings (SS) up to 300 mV/dec. ► Excellent step coverage on either finFETs and vertically-stacked SiNW FETs. ► Functional inverter and logic NAND operations are obtained.