A high performance dual clock elastic FIFO network interface for GALS NoC

A dual clock register based elastic First-In First-Out Architecture is presented for Globally Asynchronous Locally Synchronous (GALS) Network on Chip interface. The FIFO is designed using synchronous elastic methods, facilitating its synthesis with commercial CAD tools. This FIFO supports arbitrary phase and frequency for read and write operations and prepares safe data transmission between different clock domains. The presented structure can be easily used as an interface between synchronous or asynchronous GALS modules. The FIFO is simulated and analyzed with 32 nm PTM library in HSPICE. Metastability, process variation, throughput, power, area, delay and maximum frequency are analyzed. Results show elastic FIFO power delay product (PDP) is 23% less than similar synchronous FIFOs. Our proposed elastic FIFO has double capacity while the area is almost the same. The elastic FIFO tolerates better high variability and can preserve its functionality by 5% in average more than the DSPIN synchronous FIFO in presence of variation.