Analytical model of surface potential and threshold voltage in gate-drain overlap FinFET

A gate-drain overlapped FinFET, which provides low leakage current (IOFF), high ION current, and high ION/IOFF ratio with low subthreshold swing (SS), is proposed. To have better physical inside of the proposed structure, a 3-D analytical model of surface potential is derived by solving Poisson's equation in the channel and overlap regions using superposition principle. Using the surface potential, a closed form expression for the threshold voltage is also derived. Both the surface potential and threshold voltage models show good agreement with TCAD simulation data for different values of channel lengths, fin heights, fin widths, gate work functions, and channel concentrations. Furthermore, the performance of the device is evaluated in digital circuit applications and interestingly, no overshoot and undershoot are observed in the transient characteristics in case of a low power inverter. Investigation shows that the gate-drain overlap region influences the device characteristics significantly.