Improving the quality of Al2O3/4H-SiC interface for device applications

The present paper focuses on the investigation of Al2O3/4H-SiC dielectric interface upon annealing, its consequent structural modifications, and the link to electrical properties. For this purpose, the test structures are prepared by depositing Al2O3, using atomic layer deposition (ALD), on low doped n-type 4H-SiC epitaxial layers. The structures are annealed from 300 °C to 1100 °C for different time duration (from 5 to 60 mins) and ambient such as, low vacuum (10−1 Torr), N2, and N2O. The structural studies on these samples are conducted using synchrotron-based high resolution x-ray photoelectron spectroscopy (HR-XPS), lab-based XPS, time of flight elastic recoil detection analysis (ToF-ERDA), and time of flight medium energy ion scattering (ToF-MEIS). The electrical response of capacitive structures is monitored through capacitance voltage (CV) measurements for as-deposited and annealed structures. It is found that the annealing at high temperatures, such as 1100 °C, and in N2 or N2O environment, improves the dielectric properties due to the introduction of a thin layer of about 1 nm stable SiO2 between the Al2O3 and 4H-SiC.