Silicon-on-Ferroelectric Insulator field effect transistor (SOFFET): Partially depleted structure for sub-60Â mV/decade applications

This paper presents the concept of a new field effect transistor (FET) named a Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor (PD-SOFFET). Our design proposes to utilize the negative capacitance (NC) of ferroelectric material in a partially depleted silicon-on-insulator (PD-SOI) device structure. We suggest to substitute the buried insulator oxide (SiO2) inside the SOI substrate with a ferroelectric material, which converts it to the Silicon-on-Ferroelectric Insulator (SOF) substrate. The proposed integration of a ferroelectric material into the body of the MOSFET device will provide the required NC effect to overcome the fundamental thermionic barrier of the current and emerging FETs. This new SOFFET device would provide enhanced device gain, speed and channel conduction. A theoretical model is developed to validate the concept of the new device, which can lower the subthreshold swing (S) below the theoretical minimum S=60 mV/decade that is imposed by the thermodynamic limit (kT/q) of the FET devices. Analytical models have been derived to show that the subthreshold swing and the threshold voltage of the proposed device depend on the thicknesses of ferroelectric insulator and gate oxide, and the doping profile of the silicon body. It has been demonstrated that by carefully optimizing different geometric and electrical parameters the proposed PD-SOFFET can provide S value significantly below 60 mV/decade.