کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
7150485 | 1462192 | 2018 | 22 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Electrical characterization of vertically stacked p-FET SOI nanowires
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
سایر رشته های مهندسی
مهندسی برق و الکترونیک
پیش نمایش صفحه اول مقاله
![عکس صفحه اول مقاله: Electrical characterization of vertically stacked p-FET SOI nanowires Electrical characterization of vertically stacked p-FET SOI nanowires](/preview/png/7150485.png)
چکیده انگلیسی
This work presents the performance and transport characteristics of vertically stacked p-type MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. The conventional procedure to extract the effective oxide thickness (EOT) and Shift and Ratio Method (S&R) have been adapted and validated through tridimensional numerical simulations. Electrical characterization is performed for NWs with [1â¯1â¯0]- and [1â¯0â¯0]-oriented channels, as a function of both fin width (WFIN) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15â¯nm gate length, for both orientations. Effective mobility is found around two times higher for [1â¯1â¯0]- in comparison to [1â¯0â¯0]-oriented NWs due to higher holes mobility contribution in (1â¯1â¯0) plan. Improvements obtained on ION/IOFF by reducing WFIN are mainly due to subthreshold slope decrease, once small and none mobility increase is obtained for [1â¯1â¯0]- and [1â¯0â¯0]-oriented NWs, respectively.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Solid-State Electronics - Volume 141, March 2018, Pages 84-91
Journal: Solid-State Electronics - Volume 141, March 2018, Pages 84-91
نویسندگان
Bruna Cardoso Paz, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello,