Nanotechnology copper interconnect processes integrations for high aspect ratio without middle etching stop layer

As design rules for interconnection tend to result in the reduction of silicon chip size, devices have been miniaturized and fabrication processes have become more complex. Implementation of Cu and low dielectric constant (low-k) materials in the manufacturing process integration require a complete understanding of these process characteristics and the challenges that appear during the hard mask based dual damascene approach. To create highly reliable electrical interconnects, the interfaces between the Cu metal and low-k must be optimized during the lithography, etching, ashing and copper processes. For higher aspect ratios interconnect profiles, however this approach leads to increased sidewall roughness and undercut. To suppress problems in the fabrication processes, the balance of the processes integration should be quantitatively and instantaneously controlled to the optimum manufacturing technologies. These process characteristics and manufacturing mechanism optimization will also be discussed.