Performance-augmented storage capacitor by reduced resistance of polysilicon electrode for trench DRAM

The influence of process condition on the resistivity of the arsenic-doped polysilicon electrode for the cell capacitors in trench DRAM was investigated. Rather than the arsine flow, it is found that the thickness of the undoped amorphous silicon plays a vital role in determining the overall resistivity. When the total polysilicon thickness is kept unchanged, moderately increasing the thickness of the lower two undoped amorphous silicon would engender a reduced resistivity while moving the arsenic peak location away from the polysilicon/storage dielectric interface, which is critical in leakage current suppression. With these improved properties, less bit line coupling (BLC) loss from the characterization on DRAM product is observed. The result of this study is quite important for trench DRAM manufacturer to enhance product yield before the technology of metal electrode is mature.