Effect of high-k and vacuum dielectrics as gate stack on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET

• Asymmetric gate dielectric is proposed to enhance the hot carrier reliability.
• Full-Range drain current model is presented for vacuum oxide based junctionless transistor.
• Superposition technique has been used in this analysis.
• The design will be helpful for high reliable circuit application.

In this paper, the impact of asymmetric gate stack architecture using a combination of vacuum and high-k dielectrics on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET has been investigated. A comparative evaluation of short channel effects (SCEs) for various device structures has also been carried out with figure of merit (FOM) metrics such as electric field, electron temperature, drain current (Ids), and drain induced barrier lowering (DIBL). A two-dimensional analytical model has been developed for the asymmetric architecture using Poisson’s equation in cylindrical coordinates assuming a parabolic potential profile. It is observed that the asymmetric gate stack device demonstrates effectiveness in suppressing hot carrier degradation and short channel effects along with improving the current drivability of the device as compared to the other device configurations. The analytical results have been verified with the simulated data obtained from ATLAS 3-D device simulator.