Keywords: پشته دروازه; Charge plasma; Gate stack; Dual material; Junctionless transistor (JLT); Analog FOMs;
مقالات ISI پشته دروازه (ترجمه نشده)
مقالات زیر هنوز به فارسی ترجمه نشده اند.
در صورتی که به ترجمه آماده هر یک از مقالات زیر نیاز داشته باشید، می توانید سفارش دهید تا مترجمان با تجربه این مجموعه در اسرع وقت آن را برای شما ترجمه نمایند.
در صورتی که به ترجمه آماده هر یک از مقالات زیر نیاز داشته باشید، می توانید سفارش دهید تا مترجمان با تجربه این مجموعه در اسرع وقت آن را برای شما ترجمه نمایند.
Optimization of gate-stack in junctionless Si-nanotube FET for analog/RF applications
Keywords: پشته دروازه; Interfacial layer thickness; Outer gate length; Gate stack; Silicon nanotube;
Mechanism of mobility enhancement in Ge p-channel metal-oxide-semiconductor field-effect transistor due to introduction of Al atoms into SiO2/GeO2 gate stack
Keywords: پشته دروازه; Ge; MOSFET; Gate stack; Mobility enhancement; Defect termination;
Study of 6T SRAM cell using High-K gate dielectric based junctionless silicon nanotube FET
Keywords: پشته دروازه; Gate stack; SiNT FET; Interfacial layer thickness; 6T SRAM;
Effect of FIBL in-conjunction with channel parameters on analog and RF FOM of FinFET
Keywords: پشته دروازه; Channel parameters; Fringing field; High-K dielectric; Gate stack; Intrinsic dc gain;
Analog/RF performance analysis of channel engineered high-K gate-stack based junctionless Trigate-FinFET
Keywords: پشته دروازه; Junctionless trigate-FinFET; Gate stack; Interfacial layer thickness; Intrinsic dc gain;
Effect of spacer dielectric engineering on Asymmetric Source Underlapped Double Gate MOSFET using Gate Stack
Keywords: پشته دروازه; Source underlap; Gate Stack; Analog and RF analysis; Non Quasi Static; Single stage amplifier;
Effect of high-k and vacuum dielectrics as gate stack on a junctionless cylindrical surrounding gate (JL-CSG) MOSFET
Keywords: پشته دروازه; Junctionless transistor (JLT); Vacuum dielectric; High-k dielectric; Gate stack; Cylindrical surrounding gate (CSG)
Impact of Lateral Straggle on the Analog/RF Performance of Asymmetric Gate Stack Double Gate MOSFET
Keywords: پشته دروازه; Gate stack; Asymmetric underlap; Source underlap; Lateral straggle; Analog and RF performance; Non-quasi-static effects (NQS)
Impact of Asymmetric Dual-k Spacer in the Underlap Regions of Sub 20Â nm NMOSFET with Gate Stack
Keywords: پشته دروازه; Gate Stack; Dual-k spacer; Fringing fields; ION; Intrinsic capacitances;
Impact of gate material engineering(GME) on analog/RF performance of nanowire Schottky-barrier gate all around (GAA) MOSFET for low power wireless applications: 3D T-CAD simulation
Keywords: پشته دروازه; ATLAS-3D; Dual material gate; Gate all around; Gate stack; Gate material engineered (GME); Schottky-barrier (metal) source/drain; Wireless applications;
Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET
Keywords: پشته دروازه; DG-MOSFET; HKMG; Gate Stack; SCEs; Analog and RF FOMs
Two dimensional simulation and analytical modeling of a novel ISE MOSFET with gate stack configuration
Keywords: پشته دروازه; Device simulation; Dielectric pocket; FIBL; Gate stack; Voltage Doping Transformation
Deposition and characterization of MgO/Si gate stacks grown by molecular beam epitaxy
Keywords: پشته دروازه; Oxide thin films; High K dielectric; Gate stack
Some issues in advanced CMOS gate stack performance and reliability
Keywords: پشته دروازه; CMOS; Gate Stack; Reliability
Modeling complexity of a complex gate oxide
Keywords: پشته دروازه; High-k dielectric; Theory; Density functional; Oxygen vacancy; Band alignment; Gate stack; CMOS
Practical realization of dual-gate-oxide technology concept using ultra-shallow nitrogen r.f. plasma implantation with plasma and thermal oxidation
Keywords: پشته دروازه; CMOS; Dual gate oxide; Gate stack; Oxynitride; Plasma implantation;
Interface optimization for poly silicon/tungsten gates
Keywords: پشته دروازه; Gate stack; Interface resistance; PVD; Sputtering; GC
Application of r.f. plasma ultrashallow nitrogen ion implantation for pedestal oxynitride layer formation
Keywords: پشته دروازه; CMOS; Gate stack; Pedestal oxynitride; Plasma implantation;
Physics-based 1/f noise model for MOSFETs with nitrided high-κ gate dielectrics
Keywords: پشته دروازه; High-κ dielectric; Gate stack; Unified Noise Model; MOSFET; 1/f noise; Interface traps
HfO2 as gate dielectric on Ge: Interfaces and deposition techniques
Keywords: پشته دروازه; Hafnium oxide; Germanium; Metal–oxide–semiconductor structures; Gate stack; Atomic layer deposition; Metal organic vapor deposition; Molecular beam deposition
Low-temperature conductance measurements of surface states in HfO2–Si structures with different gate materials
Keywords: پشته دروازه; High-k dielectrics; Gate stack; Interface state density; G/ω measurements