Effect of spacer dielectric engineering on Asymmetric Source Underlapped Double Gate MOSFET using Gate Stack

In this paper, the use of high-k spacers in a source underlapped nMOSFET is explored. The effects have been reported by varying the dielectric constant of the spacer from 3.9 to 22.5 and the study includes a comparison of analog parameters such as transconductance, transconductance generation factor, intrinsic gain, and RF parameters such as parasitic capacitances, resistances, and cut-off frequency. The RF parameters are calculated using the Non-Quasi Static (NQS) Approach which is required for sub 20 nm technology node. The device with high-k spacers features an improvement of 33% in DIBL, significantly increases the on current and reducing the off current by 60%. However, there is a slight compromise in the RF performance of the device, owing to an increase in intrinsic capacitance by about 0.35 fF. The Voltage Transfer Characteristics (VTC) and AC gain analysis of the circuit is also done in this paper. The circuit performance using single stage amplifier with the proposed device as the driver MOS has been analysed. High-k spacers also account for 19% improvement in small signal gain when used in a single stage amplifier circuit.