Charge-plasma based dual-material and gate-stacked architecture of junctionless transistor for enhanced analog performance

Charge plasma based doping-less dual material double gate (DL-DMDG) junctionless transistor (JLT) is proposed. This paper also demonstrate the potential impact of gate stacking (GS) (high-k + Sio2) on DL-DMDG (DL-GSDMDG) JLT device. The efficient charge plasma is created in an intrinsic silicon film to form n + source/drain (S/D) by selecting proper work function of S/D electrode which helps to minimize threshold voltage fluctuation that occurs in a heavily doped JLT device. The analog performance parameters are analyzed for both the device structures. Results are also compared with conventional dual material double gate (DMDG) and gate stacked dual material double gate (GSDMDG) JLT devices. A DL-DMDG JLT device shows improved early voltage (VEA), intrinsic gain (AV = gm/gDS) and reduced output conductance (gDS) as compared to conventional DMDG and GSDMDG JLT devices. These values are further improved for DL-GSDMDG JLT. The effect of control gate length (L1) for a fixed gate length (L = L1+L2) are also analyzed.