کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
7117750 | 1461367 | 2018 | 5 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Optimization of gate-stack in junctionless Si-nanotube FET for analog/RF applications
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موضوعات مرتبط
مهندسی و علوم پایه
سایر رشته های مهندسی
مهندسی برق و الکترونیک
پیش نمایش صفحه اول مقاله
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چکیده انگلیسی
In this work, gate-stack based junctionless Si-nanotube (JLSiNT) FET is studied to investigate the effect of high-K gate dielectric material in-conjunction with interfacial layer thickness (TI) and outer gate length (Lg) on analog/RF figures of merit (FOM) of the device. With the use of high-K gate dielectric intrinsic dc gain (AV), cut-off frequency (fT), and maximum oscillation frequency (fMAX) degrades. It is observed that the degradation in analog/RF performance when high-K gate dielectrics are used, can be improved by taking higher TI. Furthermore, it is also observed that by using optimal TI (0.7â¯nm), the variation in ÎAV (AV(K=3.9) - AV(K=40)), ÎfT (fT(K=3.9) - fT(K=40)), and ÎfMAX (fMAX(K=3.9) - fMAX(K=40)) FOMs are almost invariant when outer gate length (Lg) is scaled down from 30â¯nm to 15â¯nm. Therefore, it is pertinent to consider higher interfacial layer thickness (~0.7â¯nm) and lower outer gate length (~ 15â¯nm) while designing gate-stack based JLSiNT-FET for analog/RF applications.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Materials Science in Semiconductor Processing - Volume 80, 15 June 2018, Pages 63-67
Journal: Materials Science in Semiconductor Processing - Volume 80, 15 June 2018, Pages 63-67
نویسندگان
Shubham Tayal, Ashutosh Nandi,