|کد مقاله||کد نشریه||سال انتشار||مقاله انگلیسی||ترجمه فارسی||نسخه تمام متن|
|543333||871653||2014||10 صفحه PDF||سفارش دهید||دانلود رایگان|
In this paper, the electrical characteristics of dielectric stack ISE MOSFET have been discussed in conjunction with long term requirements of ITRS. The key factors affecting the device performance and the physics behind it are also scrutinized. In addition, an analytical model using a computationally efficient Evanescent Mode Analysis (EMA), supplemented by extensive device simulation, has been presented. Drain Induced Barrier Lowering (DIBL) has been included in the model in a physically consistent manner, using Voltage Doping Transformation (VDT) method. The obtained analytical results have been verified by ATLAS 2D: device simulation software. For ultra thin gate dielectric oxide, analytical description of invoking quantum effects has also been given consideration in this paper.
Journal: Microelectronic Engineering - Volume 86, Issue 10, October 2009, Pages 2005–2014