Identification of Si film traps in p-channel SOI FinFETs using low temperature noise spectroscopy

The aim of this study is to analyse the excess low frequency noise from 100 K up to room temperature in p-channel triple-gate standard and strained FinFET transistors fabricated on silicon on insulator (SOI) substrates. The low frequency noise measurements as a function of temperature can be successfully used as a non-destructive device characterisation tool in order to evaluate the quality of the silicon film and to identify traps induced during the device processing. Several identified traps which can be related to boron and carbon, in particular for strained substrate devices, were observed.