A new non-volatile memory architecture embedding microbatteries to improve data retention criterion

• We demonstrate the feasibility of a mixed battery-memory cell structure and validate the concept.
• We perform a TCAD simulation of the program, erase and read steps.
• We obtain a viable 3.2 V programming window before process optimization.
• We propose a promising solid-state battery to be embedded in the Flash process.
• More than 10 Gbytes can be connected to a single battery cell.

In this paper, we propose an original Flash-type structure, integrating microbatteries in the circuitry to localize the stored charge over a thick oxide during the retention phase and thus improving this key reliability criterion. We first describe the proposed architecture using two lateral gates and different programming and erasing schemes. Then we develop a full TCAD simulation of our structure showing the feasibility of this cell with a viable 3.2 V programming window before process optimization. Moreover, through recent advances in micro–nanobatteries, we demonstrate that we are able to integrate them in the circuitry to maintain 10 Gbytes worth of data for more than ten years.