Strained Si and SiGe tunnel-FETs and complementary tunnel-FET inverters with minimum gate lengths of 50 nm

In this work we experimentally demonstrate a novel method to fabricate short channel complementary planar strained Si (sSOI) TFETs with improved tunneling junctions by implantation into silicide method (IIS). For the first time we have successfully fabricated both, n- and p-type TFETs with high on-currents using ultra thin sSOI structures. We demonstrate all Si complementary TFET (C-TFET) inverters with a gain as large as 60 at VDD = 2 V and sharp transitions down to very low VDD = 0.2 V. The first transient response analysis of the NW C-TFET inverter showed a propagation delay of tp < 20 ns for LG = 50 nm. Nanowire array devices with improved electrostatic control compared to a planar device geometry with 15 nm wires were fabricated using Si1−xGex with x = 35% and x = 50% showing improved ION with increasing Ge concentration. As compared to SiGe homojunction devices, Si1−xGex/Si heterostructure NW TFETs show improved ION/IOFF ratio up to 8 orders of magnitude and reduced trap assisted tunnelling (TAT) due to in situ source doping.