Low power options for 32 nm always-on SRAM architecture

The SRAM 6T bit-cell suffers many limitations in advanced technology nodes among which variability effects. Various alternatives have been experimented and the paper focuses on the 5T-Portless bit-cell. Read and write operations are operated by varying voltage conditions. Literature regarding 32 nm CMOS for Portless SRAM has been reviewed and improvements are presented. The bit-cells are arranged in matrix to permit a current-mode read operation as opposed to voltage-based sensing techniques. Thus safety and stability of the bit-cell operation is established without constraints on memory periphery. The current-mode operation enables a significant gain in dynamic power consumption beneficial to always-on memories. The paper presents different existing solutions to limit the power consumption and their limitations in thin CMOS technologies. The portless bit-cell is presented as a low power architecture alternative to 6T-SRAM. A matrix test-chip is currently under fabrication in bulk CMOS 32 nm.

Research highlights
► Extension of 5T Portless Embedded-SRAM to 32 nm CMOS and beyond.
► Original operating is presented and the current-mode operation is considered.
► The proposed SRAM is dedicated for true always-on, very low power applications.
► Hard-line copy technique is introduced to as an alternative to the current sensors.
► Low power Multiplexed architecture is developed with the hard-line copy technique.