کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
747559 | 894538 | 2006 | 6 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
A new CMP-less integration approach for highly scaled totally silicided (TOSI) gate bulk transistors based on the use of selective S/D Si epitaxy and ultra-low gates
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
سایر رشته های مهندسی
مهندسی برق و الکترونیک
پیش نمایش صفحه اول مقاله

چکیده انگلیسی
In this paper, we present an innovative way of fabricating MOS transistors with totally Ni-silicided (Ni-TOSI) gates without any CMP step before the full gate silicidation process. The combination of the use of a hard-mask-capped ultra-low initial Si gate with a selective S/D epitaxy step enables us to perform the total gate and junction silicidation in one single step similarly to a standard MOS flow. Full gate silicidation and well-controlled junction silicidation is achieved down to minimum gate lengths of 40 nm. Moreover, we show that the TOSI PMOS device performances are compatible with the 45 nm-node LP requirements. Reliability data is added demonstrating that no additional breakdown mechanisms occur after the TOSI process.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Solid-State Electronics - Volume 50, Issue 4, April 2006, Pages 620–625
Journal: Solid-State Electronics - Volume 50, Issue 4, April 2006, Pages 620–625
نویسندگان
Markus Müller, Alexandre Mondot, Delphine Aimé, Benoît Froment, Alexandre Talbot, Julien-Marc Roux, Guillaume Ribes, Yves Morand, Sophie Descombes, Pascal Gouraud, François Leverd, Simone Pokrant, Alain Toffoli, Thomas Skotnicki,