Integrating intrinsic parameter fluctuation description into BSIMSOI to forecast sub-15 nm UTB SOI based 6T SRAM operation

Novel device architectures such as ultra-thin body silicon-on-insulator (UTB SOI) MOSFETs which are more resistant to some of the sources of intrinsic parameter fluctuations are expected to play an increasingly important role beyond the 45 nm technology node. Apart from reduced device variability UTB SOI SRAM would benefit considerably from the superior electrostatic integrity and reduced junction capacitance compared to bulk MOSFETs. Furthermore, a steeper sub-threshold slope permits trade off between performance and power consumption for SRAM design. To fully realise performance benefits of UTB SOI based circuits a statistical circuit simulation methodology which can fully capture intrinsic parameter fluctuation information into BSIMSOI compact model has been developed. The impact of body thickness variations on 6T SRAM static noise margins, read and write characteristics has been investigated for well scaled UTB SOI devices with physical channel length in the range of 10–5 nm.