کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
747680 1462236 2014 4 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Trans-capacitance modeling in junctionless gate-all-around nanowire FETs
موضوعات مرتبط
مهندسی و علوم پایه سایر رشته های مهندسی مهندسی برق و الکترونیک
پیش نمایش صفحه اول مقاله
Trans-capacitance modeling in junctionless gate-all-around nanowire FETs
چکیده انگلیسی


• Junctionless nano-wire is one of the most promising alternative architecture for CMOS.
• Some works have been done via numerical simulations.
• An analytical and explicit model of trans-capacitance matrix is investigated in this work.
• This paper is an important stage to include AC analysis in junctionless nanowire FETs.

In this brief, we derive an analytical model for trans-capacitances in Junctionless Nanowire Field Effect Transistors (JL NW FET). As for static operation, we show that a complete small signal capacitance network can be built upon an equivalence scheme recently pointed out between JL NW FET and its double gate counterpart for which such a model has been proposed. This approach is validated by 3D Technology Computer Aided Design simulations and bridges the gap between the nanowire junctionless device and its application in circuits.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Solid-State Electronics - Volume 96, June 2014, Pages 34–37
نویسندگان
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