کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
747771 1462240 2014 7 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Device design assessment of 4H–SiC n-IGBT – A simulation study
موضوعات مرتبط
مهندسی و علوم پایه سایر رشته های مهندسی مهندسی برق و الکترونیک
پیش نمایش صفحه اول مقاله
Device design assessment of 4H–SiC n-IGBT – A simulation study
چکیده انگلیسی


• A closely matched device model for a recently demonstrated 4H–SiC IGBT is developed.
• IGBT operation is studied for high temperature up to 600 K.
• Interface charge has very small effect in controlling the 4H–SiC IGBT properties.
• The design parameters of IGBT such as JFET width and gate length are investigated in detail.
• A drift layer thickness and doping to acquire higher blocking voltage are investigated.

A theoretical design assessment is presented using two dimensional numerical computer aided design (TCAD) tool for 15–20 kV 4H–SiC IGBTs. Physical parameters of the layer structures such as drift layer thickness, doping in the drift layer, JFET region width and interface charges underneath the gate region are varied to predict the device performance. Performance is further assessed at different temperatures and with different carrier lifetime in the drift layer. Using identical set of physical device parameters (doping, thicknesses), simulated structure was first calibrated with the experimental data. Simulations show that a minority carrier lifetime in the drift layer of 1.0–1.6 μs produces a close match with the experimental device. An on-resistance first decays with temperature (i.e., increased in ionization level, and increase in minority carrier lifetime), stays nearly constant with further increase in the temperature (may be all carriers are now fully ionized and increase in carrier lifetime is compensated with decrease in the carrier mobility) and finally increases linearly with temperature (>450 K) due to decrease in the carrier mobility. A significant increase in the forward voltage drop is observed with the presence of interface trap charges. Increasing JFET region width slightly decreases the forward on-state voltage. A drift layer of at least 175 μm thick with a doping concentration of < 2.0 × 1014 cm−3 is required to get a blocking voltage of 20 kV for 4H–SiC IGBTs assuming a minority carrier lifetime of 1 μs in the drift layer.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Solid-State Electronics - Volume 92, February 2014, Pages 5–11
نویسندگان
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