Design, fabrication and test of novel LDMOS-SCR for improving holding voltage

• A novel structure is achieved by inserting P+ slots into the polygate of LDMOS-SCR.
• Adjusting the area of inserting P+ slots can drop the parasitic npn current gain.
• Measurement shows that the Vh of the proposed structure has 45.29% increment.

A novel structure, which is achieved by inserting P+ slots into the polygate of traditional LDMOS-SCR, has been designed to improve the holding voltage. The proposed structure called GateDot was fabricated in 0.5 μm 18 V CDMOS process. In this study, comparative analysis is carried out to make detailed comparisons between conventional LDMOS-SCR and the new proposed structure. GateDot not only maintains superiorities of low trigger voltage and strong capability of shunting ESD current in conventional LDMOS-SCR structure, but also increases the holding voltage greatly. To verify its advantages, theoretical analysis and TCAD device simulations were provided during the course of research. TLP (Transmission Line Pulse) test has been done and the results show that the holding voltage can effectively increase from 7.00 V to 10.17 V, 45.29% increment compared to traditional LDMOS-SCR, which is highly appeal to the simulation results.