|کد مقاله||کد نشریه||سال انتشار||مقاله انگلیسی||ترجمه فارسی||نسخه تمام متن|
|747916||1462225||2015||10 صفحه PDF||سفارش دهید||دانلود رایگان|
• Sub-threshold drain current model for Double Gate Junctionless Transistor.
• Impact S/D region length on the analog and digital performance DG-JL transistor has been investigated.
• High-k spacer layer improved the device characteristics due to better gate controllability.
• Evanescent Mode Analysis along with the Schwarz–Christoffel transformation is used to evaluate channel potential.
In the present work, the performance of DG-JL transistor has been analysed using analytical modeling scheme as well as 3D device simulation technique. Thus an advance two dimensional analytical sub-threshold drain current model for Double Gate Junctionless (DG-JL) Transistor is presented in this work by considering the impact of fringing field from the gate to source/drain region using conformal mapping technique. The results obtained from proposed model have been verified with the ATLAS 3D device simulation software results. The relevant Short Channel Effect parameters like threshold voltage roll off, Drain Induced Barrier Lowering (DIBL) and Subthreshold Slope (S) are also evaluated using modeling scheme. In addition to this, the suitability of DG-JL Transistor for low voltage digital and analog applications has been investigated through exhaustive device simulation using ATLAS 3D device simulation software only. In essence, this work provides the dependencies of the device performance on the physical device parameters of DG-JL transistor for its assessment for better digital and analog operation.
Journal: Solid-State Electronics - Volume 107, May 2015, Pages 20–29