Electrical characterization of thulium silicate interfacial layers for integration in high-k/metal gate CMOS technology

This work presents a characterization of the electrical properties of thulium silicate thin films, within the scope of a possible application as IL (interfacial layer) in scaled high-k/metal gate CMOS technology. Silicate formation is investigated over a wide temperature range (500–900 °C) through integration in MOS capacitor structures and analysis of the resulting electrical properties. The results are compared to those obtained from equivalent devices integrating lanthanum silicate interfacial layers. The thulium silicate IL is formed through a gate-last CMOS-compatible process flow, providing IL EOT of 0.1–0.3 nm at low formation temperature and interface state density at flatband condition below 2 × 1011 cm−2 eV−1. The effects of a possible integration in a gate-first process flow with a maximum thermal budget of 1000 °C are also evaluated, achieving an IL EOT of 0.2–0.5 nm, an interface state density at flatband condition ∼1 × 1011 cm−2 eV−1 and a reduction in gate leakage current density of one order of magnitude compared to the same stack without IL.