Formation of 30-V power DMOSFET's by implementing p-counter-doped region within n-type drift layer

Formation of 30-V power DMOSFET device by implementing p-counter-doped region within n-drift layer has been proposed. The implementation of p-counter-doped region within the n-drift region may provide charge compensation, thus reducing electric field at the same bias voltage. A proper p-counter-doping implantation condition may be employed to largely enhance the blocking voltage, without considerable degradation of on-state characteristics. Accordingly, as compared to the conventional DMOSFET device, the DMOSFET device with p-counter-doped region can employ a larger doping concentration of n-drift layer to lower the series resistance in the drift layer, without degrading the blocking voltage. As a result, for a 30-V DMOSFET device, the usage of p-counter-doped region within the n-drift layer can cause a specific on-state resistance of only about 0.44 mΩ cm2 that is 10% smaller than that for the conventional device.