Tunnel FET with non-uniform gate capacitance for improved device and circuit level performance

We report the significant improvement obtained by a non-uniform gate capacitance made by appropriate combination of high-k and low-k regions over the tunneling and the channel regions of a heterostucture TFET (called HKLKTFET). In addition to significantly enhanced ION and subthreshold swing, we find that this structure offers great improvements for the dynamic switching energy (66% saving) and propagation delay (∼3× fast operation) compared to a heterostructure TFET (HeTFET) due to the reduction of the Miller effect. We compare and benchmark the proposed device against a 65 nm low stand-by power (LSTP) CMOS technology, and we show that at a supply voltage of VDD = 0.4 V, TFETs can have smaller propagation delays compared to CMOS operating in the subthreshold region. Higher cut-off frequency (∼3×) and bandwidth for analog applications is observed in circuit-level simulations.

► A non-uniform gate oxide stack proposed for TFET structures.
► TCAD simulations reveal drastic reduction in device capacitance for non-uniform gate stacks due to utilization of low-k oxide.
► Investigation of circuit-level figures of merit via SPICE simulation.
► Circuit level performance improvement for non-uniform structure due to the reduction of the capacitance.