Compact modeling of STT-MTJ devices

STT-MTJ is a promising device for future high-density and low-power integrated systems. To enable design exploration of STT-MTJ, this paper presents a fully compact model for efficient SPICE simulation. Derived from the fundamental LLG equation, the new model consists of RC elements that are compact equations of device geometry and material properties. They support transient SPICE simulations, providing necessary details beyond the macromodel and enable resilient memory design. The accuracy of the model is validated with numerical results and published data. Scaling analysis shows the sensitivity of STT-MTJ to its geometry. We also did variability analysis with Monte Carlo simulation of the basic 1T1MTJ memory cell to study the bit error rate performance for different transistor size and programming current profile. We show that there is a tradeoff between programming energy and cell area for the same bit error rate constraint. Finally we derive the cell size that achieves minimum energy consumption for a given bit error rate constraint (primary) and latency or area constraint (secondary).