Analysis of USJ formation with combined RTA/laser annealing conditions for 28 nm high-k/metal gate CMOS technology using advanced TCAD for process and device simulation

TCAD process and device simulations are used to gain physical understanding for the integration of laser-annealed junctions into a 28 nm high-k/metal gate first process flow. Spike-RTA (Rapid Thermal Annealing) scaling used for transient enhanced diffusion (TED) suppression and shallow extension formation is investigated. In order to overcome the performance loss due to a reduced RTA, laser anneal (lsa) is introduced after Spike-RTA to form highly activated and ultra shallow junctions (USJs). In this work, the impact of different annealing conditions on the performance of NMOS and PMOS devices is investigated in terms of Vth and Ion/Ioff, considering lateral dopant diffusion and activation.

► TCAD simulations are used to model laser-annealed junctions for scaled high-k/metal gate CMOS.
► The impact of laser and spike annealing conditions on NMOS and PMOS performance is investigated.
► The short-channel behavior is correctly predicted for aggressively-scaled transistors.