MASTAR VA: A predictive and flexible compact model for digital performances evaluation of CMOS technology with conventional CAD tools

• We proposed an analytical and continuous MOSFET drain current model.
• We proposed the associated charges model accounting for parasitic capacitances.
• We obtained a predictive compact model (MASTAR VA) validated by SPICE simulations.
• We proposed an evaluation of SRAM performance with MASTAR VA for the 16 nm node.

This work presents the methodology employed in order to make the MASTAR model (Model for Assessment of CMOS Technologies And Roadmaps [1]), used within the frame of the International Technology Roadmap for Semiconductor (ITRS), compatible with conventional CAD tools. As an example, we used the updated model together with ELDO for the evaluation of digital and SRAM performance.