Integration of MOSFETs with SiGe dots as stressor material

The potentials of using silicon–germanium dots as stressor material in MOSFETs are evaluated with respect to integration in today’s production processes. Work is reviewed that has lead to the fabrication of the first experimental n-channel MOSFETs on SiGe dots, referred to as DotFETs, in a low-complexity, custom-made low-temperature process where the dot is preserved during the entire device processing. The SiGe dots were grown in large regular arrays in a Stranski–Krastanow (S–K) mode and used to induce biaxial tensile strain in a silicon capping-layer. The DotFETs are processed with the main gate-segment above the strained Si layer on a single dot. To prevent intermixing of the Si/SiGe/Si structure, the processing temperature is kept below 400 °C by using excimer-laser annealing to activate the source/drain implants that are self-aligned to a metal gate. The crystallinity of the structure is preserved throughout the processing and, compared to reference devices, an average increase in drain current up to 22.5% is obtained. The experimental results are substantiated by extensive simulations and modeling of the strain levels in capped dots and the corresponding mobility enhancement achievable with DotFETs. The concept of SiGe dots overgrown with a Si layer is also considered for use as a starting structure for silicon-on-nothing (SON) technology where the dot should be removed after the formation of the gate-stack and the strain for mobility enhancement should be preserved (and possibly increased) via the other device layers.

► DotFETs – first experimental n-channel MOSFETs fabricated on SiGe dots.
► SiGe dots grown in an S–K mode used as source of stress for mobility enhancement.
► Low-complexity, custom-made low-temperature (Tmax = 400 °C) process.
► Laser-annealed source/drain regions self-aligned to gate.
► Average increase in drain current up to 22.5%.