Investigation of gate length and fringing field effects for program and erase efficiency in gate-all-around SONOS memory cells

Gate length (LG) effects for program/erase (P/E) efficiency are investigated in a gate-all-around (GAA) SONOS structure. The experimental results show that P/E characteristics become worse at a shorter LG, and this trend is verified with numerical simulation. The down-scaling of LG gives rise to a change in the electric field in tunneling oxide and blocking oxide in the GAA–SONOS structure. For P/E efficiency, these results reveal that the fringing field via a low-k dielectric medium, which encapsulates a gate electrode as an inter-layer dielectric, favorably enhances the electric field of tunneling oxide. It also reduces the electric field of blocking oxide. Additionally, it is found that the electric field of tunneling and blocking oxide becomes more sensitive to the permittivity of the inter-layer dielectric as LG is more shortened.

► Program/erase (P/E) efficiency become worse at a shorter gate length (LG).
► Fringing field leads to a change in the electric field of oxide as LG is shortened.
► The changed electric field of oxide causes P/E efficiency degraded.
► The P/E efficiency is modulated by the permittivity of the inter-layer dielectric.